1. Field of the Invention
The present invention relates to a dynamic random access memory (hereinafter referred to as DRAM), and more particularly, it relates to a CMOS-DRAM employing a (1/2) V.sub.CC precharge system, i.e., a system of precharging bit lines at (1/2) V.sub.CC by equalizing means.
2. Description of the Prior Art
A dynamic RAM generally comprises memory cell array blocks. Each of the blocks has a plurality of memory cells, and each of the memory cells is formed by a transistor and a capacitor. As the ratio of the capacitance of a bit line to that of the capacitor of the memory cell is decreased, potential variation of the bit line in data reading is increased so that input potential difference for a sense amplifier is increased, whereby a read operation is reliably performed.
However, the memory cell size is reduced as a memory having a larger capacity is implemented with higher density of integration, whereby the memory cell capacitance is decreased while the number of memory cells connected to a bit line is increased. Therefore, the bit line is enlarged in length and the capacitance thereof is increased. Thus, the ratio of the bit line capacitance to the memory cell capacitance may be so increased that a read operation cannot be reliably performed. In order to solve such a problem, there is an attempt to divide a bit line into a plurality of blocks to reduce the ratio of the bit line capacitance to the memory cell capacitance.
FIG. 1 shows the entire structure of a conventional basic DRAM.
Referring to FIG. 1, the conventional DRAM comprises a memory part 1 including a memory cell array formed by a plurality of memory cells arrayed in the form of a matrix, a row decoder for selecting a row from the memory cell array and a column decoder for selecting a column from the memory cell array. Provided as peripheral circuits are a clock generation circuit 2 for generating various operation timing signals in response to an externally supplied clock signal RAS, an address buffer 3 for strobing externally supplied address signals A.sub.0 to A.sub.n in response to a control signal (internal RAS) from the clock generation circuit 2 to generate an internal address signal and supply the same to the row decoder and the column decoder of the memory part 1, a data input buffer 4 for receiving input data D.sub.IN in response to a control signal from the clock generation circuit 2 and transmitting the same to the memory part 1 and a data output buffer 5 for receiving data read from the memory part 1 in response to a control signal from the clock generation circuit 2 and transferring output data D.sub.OUT to the exterior.
The clock signal RAS is supplied to a terminal 10. The external address signals A.sub.0 to A.sub.n are supplied to terminals 11-0 to 11-n, respectively. The input data D.sub.IN is supplied to a terminal 12. The output data D.sub.OUT is transmitted from a terminal 13 to the exterior of the DRAM. A power terminal 14 for receiving supply voltage V.sub.CC and a ground terminal 15 connected to a ground potential V.sub.SS are further provided in order to supply operating voltage to the DRAM. The memory part 1 and the peripheral circuits are integrated on a semiconductor chip 16.
FIG. 2 shows exemplary structure of the memory part 1 of the DRAM as shown in FIG. 1.
Referring to FIG. 2, the memory cell array is divided into eight memory cell array blocks ML.sub.1, ML.sub.2, ML.sub.3 and ML.sub.4 and MR.sub.1, MR.sub.2, MR.sub.3 and MR.sub.4. A column decoder is provided for four memory cell array blocks. Namely, a column decoder CL is provided for the left memory cell array blocks ML.sub.1 to ML.sub.4 and another column decoder CR is provided for the right memory cell array blocks MR.sub.1 to MR.sub.4.
A shared sense amplifier block NSL.sub.1 is provided between the memory cell array blocks ML.sub.1 and ML.sub.2. Respective bit lines of the memory cell array blocks ML.sub.1 and ML.sub.2 are connected with each other through the shared sense amplifier block NSL.sub.1, to form one bit line. A sense amplifier block PSL.sub.1 is provided to detect and amplify information on each bit line of the memory cell array block ML.sub.1, and a sense amplifier +I/O block PIL.sub.1 is provided between the column decoder CL and the memory cell array block ML.sub.2 in order to detect and amplify information on each bit line of the memory cell array block ML.sub.2.
The information on each bit line of the memory cell array block ML.sub.1 is detected and amplified by respective amplifiers of the sense amplifier block PSL.sub.1 and the shared sense amplifier block NSL.sub.1. The information on each bit line of the memory cell array block ML.sub.2 is detected and amplified by respective amplifiers of the shared sense amplifier block NSL.sub.1 and the sense amplifier +I/O block PIL.sub.1. One of the bit lines of the memory cell array blocks ML.sub.1 and ML.sub.2 is connected to a data input/output bus through an I/O gate in the sense amplifier +I/O block PIL.sub.1 by output of the column decoder CL.
The remaining memory cell array blocks ML.sub.3 and ML.sub.4 are arranged in a similar manner to the above. Namely, a sense amplifier +I/O block PIL.sub.2 is provided between the column decoder CL and the memory cell array block ML.sub.3 and a shared sense amplifier block NSL.sub.2 is provided between the memory cell array blocks ML.sub.3 and ML.sub.4 while a sense amplifier block PSL.sub.2 is provided on the right end of the memory cell array block ML.sub.4.
The right memory cell array blocks MR.sub.1 to MR.sub.4 are arranged symmetrically to the left memory cell array blocks ML.sub.1 to ML.sub.4. A sense amplifier block PSR.sub.1 is provided for the memory cell array block MR.sub.1, and a shared sense amplifier block NSR.sub.1 is provided between the memory cell array blocks MR.sub.1 and MR.sub.2. A sense amplifier +I/O block PIR.sub.2 is provided between the memory cell array block MR.sub.2 and the column decoder CR. A sense amplifier +I/O block PIR.sub.2 is provided between the column decoder CR and the memory cell array block MR.sub.3. A shared sense amplifier block NSR.sub.2 is provided between the memory cell array blocks MR.sub.3 and MR.sub.4, and a sense amplifier block PSR.sub.2 is provided on the right end of the memory cell array block MR.sub.4. Operation of each right block is functionally similar to that of the corresponding one of the left blocks.
A row decoder RD is provided for selecting a word line (a row) from the memory cell array blocks ML.sub.1 to ML.sub.4 and MR.sub.1 to MR.sub.4.
Description is now made on the structure of a bit line part selected by one of column decoder output, i.e., the structure of an adjacent pair of memory cell array blocks and a sense amplifier provided for the same.
FIG. 3 illustrates the structure of a bit line pair and a CMOS sense amplifier part of a conventional DRAM as described in, e.g., ISSCC Digest of Technical Papers 1984, pp. 278 to 279. This DRAM employs the so-called shared sense amplifier structure in which each bit line is divided into a pair of divided bit lines to commonly share a sense amplifier with a divided bit line pair provided on both sides of the same. Although transistors of memory cells are formed by P-channel FETs and the shared sense amplifier is formed by P-channel FETs and sense amplifiers on both ends are formed by N-channel FETs in the structure described in the aforementioned literature, such FETs are reversed in conductivity type and the operation is slightly simplified in FIG. 3, for convenience of illustration.
Referring to FIG. 3, symbols MCB.sub.j1 and MCB.sub.j2 indicate memory cell array blocks, each of which includes a plurality of word lines, a plurality of divided bit line pairs, memory cells, potential difference amplifying means and equalizing means. Bit lines forming folded bit lines are divided into bit line pairs BLL.sub.j, BLL.sub.j and BLR.sub.j, BLR.sub.j respectively. Cross-coupled FETs Q.sub.j1 and Q.sub.j2 form an N-channel sense amplifier (potential difference amplifying means) NSA.sub.j, which is shared with the memory cell array blocks MCB.sub.j1 and MCB.sub.j2. Similarly cross-coupled FETs Q.sub.j5, Q.sub.j6 and Q.sub.j7, Q.sub.j8 are adapted to form P-channel sense amplifiers (potential difference amplifying means) PSA.sub.jL and PSA.sub.jR, respectively. The sources of the FETs Q.sub.j1 and Q.sub.j2 are commonly connected to the drain of an FET Q.sub.N, whose gate and source are connected to an N-channel sense amplifier driving signal S.sub.N and a ground potential V.sub.SS, respectively. The sources of the FETs Q.sub.j5, Q.sub.j6 and Q.sub.j7, Q.sub.j8 are commonly connected to the drains of FETs Q.sub.PL and Q.sub.PR respectively, while the gate and the source of the FET Q.sub.PL are connected to a P-channel sense amplifier driving signal S.sub.PL and a supply potential V.sub.CC respectively, and the gate and the source of the FET Q.sub.PR are connected to a P-channel sense amplifier driving signal S.sub.PR and a supply potential V.sub.CC, respectively.
The P-channel sense amplifier PSA.sub.jL is connected to the divided bit lines BLL.sub.j and BLL.sub.j and the P-channel sense amplifier PSA.sub.jR is connected to the divided bit lines BLR.sub.j and BLR.sub.j. Transfer gate FETs Q.sub.j11 and Q.sub.j12 are provided between the divided bit lines BLL.sub.j and BLL.sub.j and the N-channel sense amplifier NSA.sub.j while transfer gate FETs Q.sub.j13 and Q.sub.j14 are provided between the divided bit lines BLR.sub.j and BLR.sub.j and the N-channel sense amplifier NSA.sub.j. The gates of the FETs Q.sub.j11, Q.sub.j12 and Q.sub.j13, Q.sub.j14 receive the transfer signals SL and SR, respectively. FETs Q.sub.j9 and Q.sub.j10 are provided for equalizing the divided bit line pairs BLL.sub.j, BLL.sub.j and BLR.sub.j, BLR.sub.j, respectively, and the gates thereof receive equalizing signals EQ.
The divided bit lines BLR.sub.j and BLR.sub.j are connected to bus lines BU and BU, respectively, through column gate FETs Q.sub.j15 and Q.sub.j16, whose gates are connected to a column selecting signal Y.sub.j. Although a plurality of memory cells are generally connected to such divided bit lines in accordance with memory capacity, for simplicity is represented a memory cell MC.sub.ij connected to the divided bit line BLL.sub.j in FIG. 3. The memory cell MC.sub.ij is formed by a capacitor C.sub.ij and an FET Q.sub.ij, and the gate of the FET Q.sub.ij is connected to a word line WL.sub.i. An electrode of the capacitor C.sub.ij is connected to a memory cell plate potential V.sub.SG.
Description is now made on an operation of the CMOS sense amplifier structure as shown in FIG. 3 in the case of reading data "1" stored in the capacitor C.sub.ij of the memory cell MC.sub.ij, with reference to FIG. 4 showing an operating waveform diagram.
The DRAM enters an activated state on the falling edge of an external RAS signal (hereinafter referred to as Ext. RAS signal) as shown in FIG. 4. In this activated state, an external row address signal is latched in the interior of the chip on the falling edge of the Ext. RAS signal. Then the equalizing signal EQ and the transfer signal SR are turned to low levels to stop equalization of the divided bit lines BLL.sub.j, BLL.sub.j and BLR.sub.j, BLR.sub.j while separating the divided bit lines BLR.sub.j and BLR.sub.j from the N-channel sense amplifier NSA. At this time, the transfer signal SL is maintained at a high level.
Then, a potential of a word line selected in response to the row address signal latched in the chip interior goes high. It is assumed here that the word line WL.sub.i of FIG. 3 is selected. When the potential of the word line WL.sub.i thus goes high, the FET Q.sub.ij enters an ON state so that the charge stored in the capacitor C.sub.ij is transferred to the divided bit line BLL.sub.j, whereby the potential of the divided bit line BLL.sub.j exceeds the level as is equalized, i.e., (V.sub.CC -V.sub.SS)/2. Then, the sense amplifier driving signals S.sub.N and S.sub.PL are turned to high and low levels, respectively, whereby the FETs Q.sub.N and Q.sub.PL are turned on so that the N-channel sense amplifier NSA.sub.j and the P-channel sense amplifier PSA.sub.jL operate to amplify the potential difference between the divided bit lines BLL.sub.j and BLL.sub.j.
Then, the transfer signal SR again goes high so that the potentials of the divided bit lines BLL.sub.j and BLL.sub.j are transferred to the divided bit lines BLR.sub.j and BLR.sub.j. As the result, the potentials of the divided bit lines BLR.sub.j and BLR.sub.j go high and low, respectively. Then, the sense amplifier driving signal S.sub.PR goes low and the FET Q.sub.PR enters an ON state so that the P-channel sense amplifier PSA.sub.jR operates, whereby the potential of the divided bit line BLR.sub.j is raised to a higher level. Then, the column selecting signal Y.sub.j goes high so that the potentials of the divided bit lines BLR.sub.j and BLR.sub.j are transferred to the bus lines BU and BU, whereby the data "1" stored in the capacitor C.sub.ij of the memory cell MC.sub.ij is read out.
When the Ext. RAS signal goes high so that the DRAM enters an inactivated state, the potential of the selected word line WL.sub.i goes low and the FET Q.sub.ij in the memory MC.sub.cj enters an OFF state. Then the sense amplifier driving signal S.sub.N is turned to a low level and the signals S.sub.PL and S.sub.PR are turned to high levels. Further, the equalizing signals EQ and the transfer signals SL and SR are turned to high levels, whereby the divided bit lines BLL.sub.j, BLL.sub.j and BLR.sub.j and BLR.sub.j are equalized so that the respective potentials thereof are averaged to the level of (V.sub.CC -V.sub.SS)/2, while the paired divided bit lines are connected with each other at the same time.
The aforementioned various control signals are produced by circuits as shown in FIG. 5. Description is now made on the structure of each control signal producing circuit.
The equalizing signal EQ is produced by a delay circuit 51 for delaying the clock signal RAS by a predetermined time t.sub.2 and an equalizing signal generator 52 formed by a buffer for waveform-shaping output from the delay circuit 51 and outputting the same.
A word line driving signal WL.sub.i is produced by a row decoder 53. The row decoder 53 decodes an internal row address from an address buffer 54 for receiving an external address and producing an internal address to select a word line WL.sub.i, thereby to make the potential of the selected word line rise in response to a signal from a delay circuit 55 for delaying the clock signal RAS by a time t.sub.3.
The NMOS sense amplifier driving signal S.sub.N is produced by a delay circuit 56 for delaying the word line driving signal WL.sub.i by a time t.sub.4 and outputting the same and an NMOS sense amplifier driving signal generator 57 formed by a buffer for waveform-shaping output from the delay circuit 56 and outputting the same.
The transfer signal SL is produced by a left transfer signal generator 60 activated in response to a block selecting address from the address buffer 54 for generating a signal which falls in response to a signal from a delay circuit 58 for delaying the clock signal RAS by a time t.sub.1 while rising in response to output from a delay circuit 59 for delaying the NMOS sense amplifier driving signal S.sub.N by a time t.sub.6.
The transfer signal SR is produced by a right transfer signal generator 61 activated in response to a block selecting address from the address buffer 54 for generating a signal which falls in response to the output from the delay circuit 58 while rising in response to the output from the delay circuit 59.
The PMOS sense amplifier driving signal S.sub.PL is produced by a left PMOS sense amplifier driving circuit 64 activated in response to a block selecting address from the address buffer 54 for generating a signal which goes low in response to either output from a delay circuit 62 for delaying the sense amplifier driving signal S.sub.N by a time t.sub.5 or output from a delay circuit 63 for delaying the sense amplifier driving signal S.sub.N by a time t.sub.7.
The PMOS sense amplifier driving signal S.sub.PR is produced by a right PMOS sense amplifier activating circuit 65 activated by a block selecting address from the address buffer 54 for generating a signal which falls in response to either output from the delay circuit 62 or 63.
The falling timing of the sense amplifier driving signals S.sub.PL and S.sub.PR is determined by the block selecting address.
The column selecting signal Y.sub.j is produced by a column decoder 67. The column decoder 67 decodes a column address from the address buffer 54 to generate a signal Y.sub.j which rises in response to output of a delay circuit 66 for delaying the NMOS sense amplifier driving signal S.sub.N by a time t.sub.8 to select a pair of bit lines and connect the same to the data input/output buses BU and BU.
When the word line WL.sub.i in the left-side block is selected in the conventional dynamic random access memory as hereinabove described, the data stored in the memory cell is first read on the divided bit lines BLL.sub.j and BLL.sub.j, to be then transferred to the divided bit lines BLR.sub.j and BLr.sub.j. On the other hand, since the left and right divided bit line pairs BLL.sub.j, BLL.sub.j and BLR.sub.j are equalized by the same signals EQ, equalization of these divided bit line pairs is simultaneously stopped. Consequently, when a word line in the left memory block is selected, the right-side divided bit lines BLR.sub.j and BLR.sub.j enter electrically floating states after the equalizing signal EQ goes low, to be maintained in such states until the transfer signal SR again goes high. Such an interval is about 5 to 15 nsec. in general. In this interval, the left-side divided bit lines BLL.sub.j and BLL.sub.j perform a sensing operation. During the sensing operation, one of the divided bit lines BLL.sub.j and BLL.sub.j, i.e., BLL.sub.j in this case, is discharged to the ground potential V.sub.SS while the other one, i.e., BLL.sub.j in this case, is charged to the power supply potential V.sub.CC. Such sensing operation is simultaneously performed in a number of divided bit line pairs coupled to memory cells which are connected to the selected word line WL.sub.i, whereby the levels of the ground potential V.sub.SS and the supply potential V.sub.CC are varied to cause noise. The right-side divided bit lines BLR.sub.j and BLR.sub.j are in floating states at the time when such noise is caused, to be subjected to potential deviation by such noise.
When the divided bit lines BLR.sub.j and BLR.sub.j are affected by noise in a direction opposite to the potentials to be originally effected, it takes time to discharge and charge the divided bit lines BLR.sub.j and BLR.sub.j, respectively, whereby the sensing time is increased by .DELTA.t as compared with the case in which no such noise is produced, to delay the access time.
A method of equalizing a bit line pair is described in U.S. Pat. No. 4,397,003 to Wilson et al., for example. However, this prior art takes no account of a divided bit line pair or noise applied to the divided bit line pair.
As a relevant prior art, there exist U.S. patent application Ser. Nos. 014837, 020192 and 027536 by the same applicant. These prior art disclose a DRAM having a divided line pair structure and the same equalizing timing.